Items by "Riley, George"
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Riley, George and Dong, Zhenjiang and Wang, Jun and Yalamanchili, Sudhakar (2014) An Efficient Front-End for Timing-Directed Parallel Simulation of Multi-Core System. In: Seventh International Conference on Simulation Tools and Techniques.
Lertpratchya, Daniel and Riley, George and Blough, Douglas (2014) Simulating Frame-Level Bursty Links in Wireless Networks. In: Seventh International Conference on Simulation Tools and Techniques.