Design and Implementation of a High-Performance Variable Latency Integer Divider in 15nm Technology

Sujatha, G. and Ahalya, Budda and Krupa, Saladhi and Meghana, Varanasi and Kishan, Thoti and Abhisheek, B. (2025) Design and Implementation of a High-Performance Variable Latency Integer Divider in 15nm Technology. In: Proceedings of the 4th International Conference on Information Technology, Civil Innovation, Science, and Management, ICITSM 2025, 28-29 April 2025, Tiruchengode, Tamil Nadu, India, Part II.

[thumbnail of 79550.pdf] PDF
79550.pdf

Download (249kB)

Abstract

Integer division is a fundamental operation in computer arithmetic, widely used in applications such as digital signal processing, cryptography, and artificial intelligence. However, due to its inherently sequential nature, integer division often becomes a performance bottleneck in modern computing

Item Type: Conference or Workshop Item (UNSPECIFIED)
Date Deposited: 04 Mar 2026 20:19
Last Modified: 16 Apr 2026 15:53
URI: http://eprints.eai.eu/id/eprint/60195

Actions (login required)

View Item
View Item