Shanti, T and Singh, S Abhishek and Chandu, D and Prakash, K Bhanu (2025) Design and Analysis of Master Slave Flip Flop with Low Power, Reduced Delay and Area Efficiency. In: Proceedings of the 4th International Conference on Information Technology, Civil Innovation, Science, and Management, ICITSM 2025, 28-29 April 2025, Tiruchengode, Tamil Nadu, India, Part I.
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Abstract
This research introduces a power-efficient master-slave flip-flop utilizing clock gating techniques, designed and analyzed using Xilinx Vivado. The proposed approach minimizes dynamic power consumption by selectively deactivating the clock signal when the flip-flop is idle. Clock gating is utilized
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Date Deposited: | 04 Mar 2026 20:17 |
| Last Modified: | 16 Apr 2026 15:59 |
| URI: | http://eprints.eai.eu/id/eprint/60052 |
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