Usha, S and Kanthimathi, M (2024) Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations. EAI Endorsed Transactions on Scalable Information Systems.
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Abstract
Binary Three-operand adder serves as a foundation block used within security and Pseudo Random-Bit Generator (PRBG) systems. Binary Three-operand adder was designed using Carry Save Adder but this consumes more delay. Therefore, a Parallel Prefix Adder (PPA) method can be utilized for faster operat
| Item Type: | Article |
|---|---|
| Date Deposited: | 04 Mar 2026 18:29 |
| Last Modified: | 10 Apr 2026 23:08 |
| URI: | http://eprints.eai.eu/id/eprint/52706 |
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