Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs

Ravindra, J.V.R. and Srinivas, M.B. (2010) Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs. In: 2nd Internationa ICST Conference on Nano-Networks.

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Abstract

This paper presents a model order reduction technique using subspace iterative scheme for high speed coupled integrated circuit interconnects in nanometer designs. The salient feature of this technique is less complexity in computation of a few smallest poles of the reduced order model. This paper s

Item Type: Conference or Workshop Item (UNSPECIFIED)
Date Deposited: 04 Mar 2026 09:19
Last Modified: 18 Apr 2026 06:34
URI: http://eprints.eai.eu/id/eprint/5175

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