Lehtonen, Teijo and Liljeberg, Pasi and Plosila, Juha (2010) Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip. In: 2nd Internationa ICST Conference on Nano-Networks.
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Abstract
The amount of errors in future nanoscale technologies is expected to increase dramatically when compared to technologies that have line width larger than 90 nm. In nanoscale CMOS circuits fault tolerance is one of the most important design constraints to sustain system reliability at an acceptable l
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Date Deposited: | 04 Mar 2026 09:19 |
| Last Modified: | 18 Apr 2026 06:34 |
| URI: | http://eprints.eai.eu/id/eprint/5174 |
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