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Abstract
Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become increasingly stringent. New design challenges are continuously emerging, suc
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Date Deposited: | 04 Mar 2026 09:19 |
| Last Modified: | 18 Apr 2026 06:34 |
| URI: | http://eprints.eai.eu/id/eprint/5159 |
