An Efficient Fault Tolerant Routing Interconnect System for Neural NOC

kumar, Dr.A. and Reddy, Y. and Reddy, Dr.T. and Jamal, K. (2021) An Efficient Fault Tolerant Routing Interconnect System for Neural NOC. In: Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bharath University, Chennai, India.

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Abstract

Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are

Item Type: Conference or Workshop Item (UNSPECIFIED)
Date Deposited: 04 Mar 2026 14:23
Last Modified: 17 Apr 2026 08:31
URI: http://eprints.eai.eu/id/eprint/34552

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