Ijaz, Momil and Urooj, Huma and Sethi, Muhammad (2019) Implementation of NoC on FPGA with Area and Power Optimization. EAI Endorsed Transactions on Context-aware Systems and Applications.
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Abstract
On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,
size, speed, power and area. The goal of working
| Item Type: | Article |
|---|---|
| Date Deposited: | 04 Mar 2026 12:21 |
| Last Modified: | 17 Apr 2026 14:28 |
| URI: | http://eprints.eai.eu/id/eprint/24161 |
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