Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation

Oveis-Gharan, Masoud and Khan, Gul (2014) Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation. In: Seventh International Conference on Simulation Tools and Techniques.

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Abstract

In this paper, a Flexible And Accurate Network-On-chip Simulator (FAANOS) is introduced. NoC is a critical structure for system-on-chip design. We discuss the structure of its various components by presenting their details. We also provide an analytical methodology that employs the micro-architectur

Item Type: Conference or Workshop Item (UNSPECIFIED)
Date Deposited: 04 Mar 2026 10:13
Last Modified: 17 Apr 2026 20:04
URI: http://eprints.eai.eu/id/eprint/11479

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